\doxysection{SPI\+\_\+\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_s_p_i___init_type_def}{}\label{struct_s_p_i___init_type_def}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}}


SPI Configuration Structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+spi.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a5247eb0463437c9980a9d4a5300b50a5}{Mode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_ae5c132f597c806d7a1fe316023b36867}{Direction}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a24b7835dd877e1c4e55236303fa3387f}{Data\+Size}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a96922c7ff9e589ebd9611fc4ab730454}{CLKPolarity}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_ab21a458209f2588f49a2353c56f62625}{CLKPhase}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_aed541d17808213ac6f90ac7deb2bec5f}{NSS}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a1d553f90738cb633a9298d2b4d306fde}{Baud\+Rate\+Prescaler}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a8c541d8863cb62a3212b9381b5cba447}{First\+Bit}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a60db7e87bb66775df6213e4006dfd876}{TIMode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a3472de9bd9247c1d97312aff7e58e385}{CRCCalculation}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_abdaf3ccbfa4ef68cc81fd32f29baa678}{CRCPolynomial}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_ade3815f539adcdeba866ab26a5f59c99}{CRCLength}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_aab94c82883ea08f33ef383efe30347eb}{NSSPMode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_ade84e3b4f320066c60d10eccd02ae1e5}{NSSPolarity}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a736486f4bfe259356bf825d8b8c848bb}{Fifo\+Threshold}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_acddf0a9e873f8c9a05c9901f648e5920}{Tx\+CRCInitialization\+Pattern}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a0288b29c4c3c41fc06605fcee9d4c100}{Rx\+CRCInitialization\+Pattern}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a1ba4e509384f19be9854adea27a454fa}{Master\+SSIdleness}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_aa46bb96cca3eec52a44926a388dbeaf9}{Master\+Inter\+Data\+Idleness}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a142a178fe24816713e6f787424b7da46}{Master\+Receiver\+Auto\+Susp}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_a2353869659f9840f31d800e012961850}{Master\+Keep\+IOState}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___init_type_def_afa49766f8a69a21f3e866fb38770b75f}{IOSwap}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
SPI Configuration Structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_s_p_i___init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_p_i___init_type_def_a1d553f90738cb633a9298d2b4d306fde}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!BaudRatePrescaler@{BaudRatePrescaler}}
\index{BaudRatePrescaler@{BaudRatePrescaler}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{BaudRatePrescaler}{BaudRatePrescaler}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a1d553f90738cb633a9298d2b4d306fde} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Baud\+Rate\+Prescaler}

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of \doxylink{group___s_p_i___baud_rate___prescaler}{SPI Baud\+Rate Prescaler} \begin{DoxyNote}{Note}
The communication clock is derived from the master clock. The slave clock does not need to be set. 
\end{DoxyNote}
\Hypertarget{struct_s_p_i___init_type_def_ab21a458209f2588f49a2353c56f62625}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!CLKPhase@{CLKPhase}}
\index{CLKPhase@{CLKPhase}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{CLKPhase}{CLKPhase}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_ab21a458209f2588f49a2353c56f62625} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+CLKPhase}

Specifies the clock active edge for the bit capture. This parameter can be a value of \doxylink{group___s_p_i___clock___phase}{SPI Clock Phase} \Hypertarget{struct_s_p_i___init_type_def_a96922c7ff9e589ebd9611fc4ab730454}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!CLKPolarity@{CLKPolarity}}
\index{CLKPolarity@{CLKPolarity}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{CLKPolarity}{CLKPolarity}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a96922c7ff9e589ebd9611fc4ab730454} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+CLKPolarity}

Specifies the serial clock steady state. This parameter can be a value of \doxylink{group___s_p_i___clock___polarity}{SPI Clock Polarity} \Hypertarget{struct_s_p_i___init_type_def_a3472de9bd9247c1d97312aff7e58e385}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!CRCCalculation@{CRCCalculation}}
\index{CRCCalculation@{CRCCalculation}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{CRCCalculation}{CRCCalculation}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a3472de9bd9247c1d97312aff7e58e385} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+CRCCalculation}

Specifies if the CRC calculation is enabled or not. This parameter can be a value of \doxylink{group___s_p_i___c_r_c___calculation}{SPI CRC Calculation} \Hypertarget{struct_s_p_i___init_type_def_ade3815f539adcdeba866ab26a5f59c99}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!CRCLength@{CRCLength}}
\index{CRCLength@{CRCLength}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{CRCLength}{CRCLength}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_ade3815f539adcdeba866ab26a5f59c99} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+CRCLength}

Specifies the CRC Length used for the CRC calculation. This parameter can be a value of \doxylink{group___s_p_i___c_r_c__length}{SPI CRC Length} \Hypertarget{struct_s_p_i___init_type_def_abdaf3ccbfa4ef68cc81fd32f29baa678}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!CRCPolynomial@{CRCPolynomial}}
\index{CRCPolynomial@{CRCPolynomial}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{CRCPolynomial}{CRCPolynomial}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_abdaf3ccbfa4ef68cc81fd32f29baa678} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+CRCPolynomial}

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min\+\_\+\+Data = 0 and Max\+\_\+\+Data = 65535 \Hypertarget{struct_s_p_i___init_type_def_a24b7835dd877e1c4e55236303fa3387f}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!DataSize@{DataSize}}
\index{DataSize@{DataSize}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{DataSize}{DataSize}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a24b7835dd877e1c4e55236303fa3387f} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Data\+Size}

Specifies the SPI data size. This parameter can be a value of \doxylink{group___s_p_i___data___size}{SPI Data Size} \Hypertarget{struct_s_p_i___init_type_def_ae5c132f597c806d7a1fe316023b36867}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!Direction@{Direction}}
\index{Direction@{Direction}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Direction}{Direction}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_ae5c132f597c806d7a1fe316023b36867} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Direction}

Specifies the SPI bidirectional mode state. This parameter can be a value of \doxylink{group___s_p_i___direction}{SPI Direction Mode} \Hypertarget{struct_s_p_i___init_type_def_a736486f4bfe259356bf825d8b8c848bb}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!FifoThreshold@{FifoThreshold}}
\index{FifoThreshold@{FifoThreshold}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{FifoThreshold}{FifoThreshold}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a736486f4bfe259356bf825d8b8c848bb} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Fifo\+Threshold}

Specifies the FIFO threshold level. This parameter can be a value of \doxylink{group___s_p_i___fifo___threshold}{SPI Fifo Threshold} \Hypertarget{struct_s_p_i___init_type_def_a8c541d8863cb62a3212b9381b5cba447}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!FirstBit@{FirstBit}}
\index{FirstBit@{FirstBit}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{FirstBit}{FirstBit}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a8c541d8863cb62a3212b9381b5cba447} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+First\+Bit}

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of \doxylink{group___s_p_i___m_s_b___l_s_b___transmission}{SPI MSB LSB Transmission} \Hypertarget{struct_s_p_i___init_type_def_afa49766f8a69a21f3e866fb38770b75f}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!IOSwap@{IOSwap}}
\index{IOSwap@{IOSwap}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{IOSwap}{IOSwap}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_afa49766f8a69a21f3e866fb38770b75f} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+IOSwap}

Invert MISO/\+MOSI alternate functions This parameter can be a value of \doxylink{group___s_p_i___i_o___swap}{Control SPI IO Swap} \Hypertarget{struct_s_p_i___init_type_def_aa46bb96cca3eec52a44926a388dbeaf9}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!MasterInterDataIdleness@{MasterInterDataIdleness}}
\index{MasterInterDataIdleness@{MasterInterDataIdleness}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MasterInterDataIdleness}{MasterInterDataIdleness}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_aa46bb96cca3eec52a44926a388dbeaf9} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Master\+Inter\+Data\+Idleness}

Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode. This parameter can be a value of \doxylink{group___s_p_i___master___inter_data___idleness}{SPI Master Inter-\/\+Data Idleness} \Hypertarget{struct_s_p_i___init_type_def_a2353869659f9840f31d800e012961850}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!MasterKeepIOState@{MasterKeepIOState}}
\index{MasterKeepIOState@{MasterKeepIOState}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MasterKeepIOState}{MasterKeepIOState}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a2353869659f9840f31d800e012961850} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Master\+Keep\+IOState}

Control of Alternate function GPIOs state This parameter can be a value of \doxylink{group___s_p_i___master___keep___i_o___state}{Keep IO State} \Hypertarget{struct_s_p_i___init_type_def_a142a178fe24816713e6f787424b7da46}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!MasterReceiverAutoSusp@{MasterReceiverAutoSusp}}
\index{MasterReceiverAutoSusp@{MasterReceiverAutoSusp}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MasterReceiverAutoSusp}{MasterReceiverAutoSusp}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a142a178fe24816713e6f787424b7da46} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Master\+Receiver\+Auto\+Susp}

Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. This parameter can be a value of \doxylink{group___s_p_i___master___r_x___auto_suspend}{SPI Master Receiver Auto\+Suspend} \Hypertarget{struct_s_p_i___init_type_def_a1ba4e509384f19be9854adea27a454fa}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!MasterSSIdleness@{MasterSSIdleness}}
\index{MasterSSIdleness@{MasterSSIdleness}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{MasterSSIdleness}{MasterSSIdleness}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a1ba4e509384f19be9854adea27a454fa} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Master\+SSIdleness}

Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. This parameter can be a value of \doxylink{group___s_p_i___master___s_s___idleness}{SPI Master SS Idleness} \Hypertarget{struct_s_p_i___init_type_def_a5247eb0463437c9980a9d4a5300b50a5}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!Mode@{Mode}}
\index{Mode@{Mode}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Mode}{Mode}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a5247eb0463437c9980a9d4a5300b50a5} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Mode}

Specifies the SPI operating mode. This parameter can be a value of \doxylink{group___s_p_i___mode}{SPI Mode} \Hypertarget{struct_s_p_i___init_type_def_aed541d17808213ac6f90ac7deb2bec5f}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!NSS@{NSS}}
\index{NSS@{NSS}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{NSS}{NSS}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_aed541d17808213ac6f90ac7deb2bec5f} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+NSS}

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of \doxylink{group___s_p_i___slave___select___management}{SPI Slave Select Management} \Hypertarget{struct_s_p_i___init_type_def_aab94c82883ea08f33ef383efe30347eb}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!NSSPMode@{NSSPMode}}
\index{NSSPMode@{NSSPMode}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{NSSPMode}{NSSPMode}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_aab94c82883ea08f33ef383efe30347eb} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+NSSPMode}

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of \doxylink{group___s_p_i___n_s_s_p___mode}{SPI NSS Pulse Mode} This mode is activated by the SSOM bit in the SPIx\+\_\+\+CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0). \Hypertarget{struct_s_p_i___init_type_def_ade84e3b4f320066c60d10eccd02ae1e5}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!NSSPolarity@{NSSPolarity}}
\index{NSSPolarity@{NSSPolarity}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{NSSPolarity}{NSSPolarity}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_ade84e3b4f320066c60d10eccd02ae1e5} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+NSSPolarity}

Specifies which level of SS input/output external signal (present on SS pin) is considered as active one. This parameter can be a value of \doxylink{group___s_p_i___n_s_s___polarity}{SPI NSS Polarity} \Hypertarget{struct_s_p_i___init_type_def_a0288b29c4c3c41fc06605fcee9d4c100}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!RxCRCInitializationPattern@{RxCRCInitializationPattern}}
\index{RxCRCInitializationPattern@{RxCRCInitializationPattern}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{RxCRCInitializationPattern}{RxCRCInitializationPattern}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a0288b29c4c3c41fc06605fcee9d4c100} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Rx\+CRCInitialization\+Pattern}

Specifies the receiver CRC initialization Pattern used for the CRC calculation. This parameter can be a value of \doxylink{group___s_p_i___c_r_c___calculation___initialization___pattern}{SPI CRC Calculation Initialization Pattern} \Hypertarget{struct_s_p_i___init_type_def_a60db7e87bb66775df6213e4006dfd876}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!TIMode@{TIMode}}
\index{TIMode@{TIMode}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{TIMode}{TIMode}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_a60db7e87bb66775df6213e4006dfd876} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+TIMode}

Specifies if the TI mode is enabled or not. This parameter can be a value of \doxylink{group___s_p_i___t_i___mode}{SPI TI Mode} \Hypertarget{struct_s_p_i___init_type_def_acddf0a9e873f8c9a05c9901f648e5920}\index{SPI\_InitTypeDef@{SPI\_InitTypeDef}!TxCRCInitializationPattern@{TxCRCInitializationPattern}}
\index{TxCRCInitializationPattern@{TxCRCInitializationPattern}!SPI\_InitTypeDef@{SPI\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{TxCRCInitializationPattern}{TxCRCInitializationPattern}}
{\footnotesize\ttfamily \label{struct_s_p_i___init_type_def_acddf0a9e873f8c9a05c9901f648e5920} 
uint32\+\_\+t SPI\+\_\+\+Init\+Type\+Def\+::\+Tx\+CRCInitialization\+Pattern}

Specifies the transmitter CRC initialization Pattern used for the CRC calculation. This parameter can be a value of \doxylink{group___s_p_i___c_r_c___calculation___initialization___pattern}{SPI CRC Calculation Initialization Pattern} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__spi_8h}{stm32h7xx\+\_\+hal\+\_\+spi.\+h}}\end{DoxyCompactItemize}
